Recently, as large-sized contents including ultra high definition (UHD) and 3D displays have become more widespread, there is a continuous request for increasing the bandwidth of wireline communications. In addition, miniaturization of semiconductor devices constantly improves computing performance of integrated circuits, thus the demand for increasing the bandwidth in wireline communications has rapidly increased.
However, due to the physical limitations of copper lines through which data transmission is performed, there is a limit for increasing the bandwidth in wireline communications using a single copper channel. Therefore, recently, there has developed a method of obtaining a high bandwidth by transmitting high speed data in parallel by using several channels.
Meanwhile, as mobile devices such as smartphones, tablet pcs, etc. are provided, there is a request for minimizing power consumption and increasing computing performance. Since power consumption directly effects battery duration time and heat of mobile devices, in integrated circuit design, designs that focus on minimizing power consumption are actively being sought by industries and institutes.
Finally, the biggest goal is to obtain a high bandwidth by transmitting data in parallel while minimizing power consumption.
A method of transmitting and receiving data by a wireline communication is classified into two types. The first one is a forwarded clock method that transmits data and a clock including timing information of the data. The forwarded clock method has excellent noise characteristics since the method is based on exact timing information obtained from the received clock. The second one is an embedded clock method that only transmits data without a clock.
There are disadvantages for the forwarded clock method in terms of power consumption and price since the method requires an additional clock channel. Thus, the embedded clock method is preferred for the conventional wireline transceiver that does not require a high bandwidth. However, recently, in a parallel forwarded data structure that satisfies the requirement of the high bandwidth, a single clock channel is additionally used for multiple data channels, thus it is possible to distribute power consumption and price that are increased due to the clock channel. Accordingly, an attempt has been made to approach a structure that can take advantage of the forwarded clock method.
A wireline communication receiver functions to recover a received signal that is deformed and distorted by several external factors while passing a copper channel to an accurate signal such that the received signal is used by an integrated circuit without error. Herein, it is the core of technology to sample the received signal at the timing where data is not mostly distorted. It is generally known that sampling at the center of the data has the best performance. For this, a method of removing timing skew that is generated between the data and the clock is used.
A structure that is the most widely used receiver is based on a voltage-controlled oscillator (VCO). In the above structure, each of data lanes needs a self-generated clock generated from the voltage-controlled oscillator, thus the structure is a very advantageous for the receiver using the embedded clock method that includes a single data channel. In addition, it is easy to design one receiver and then expand it to several since each of data channels are independently operated. Thus, the structure is widely used for a receiver with a parallel structure including multiple data channels due to an easy design thereof.
However, in the parallel structure, the receiver includes multiple voltage-controlled oscillators. The use of multiple voltage-controlled oscillators consumes large amounts of power and require a large area, thus it is very disadvantageous in terms of cost competitiveness and power consumption. In addition, interference (injection locking/pulling) between the oscillators degrades performance of the receiver and operation thereof cannot be guaranteed in severe cases.
In an effort to solve the above problems, in the parallel structure, a structure using a circuit based on a phase interpolator is used. The above structure uses a single voltage-controlled oscillator, or uses a delay-locked loop (DLL) without using the voltage-controlled oscillator and recovers data and a clock by additionally using the phase interpolator circuit. In the above structure, there is no interference generated between the voltage-controlled oscillators, but the phase interpolator circuit consumes large power and is difficult to design, thus the structure is very disadvantageous in terms of cost competitiveness and design time.
Meanwhile, jitter tolerance is the most important performance indicator to show the operating performance of the receiver. Herein, jitter is an indicator showing noise on a time axis. In the conventional receiver based on an oscillator, a frequency range of jitter tolerance is limited, or the range may greatly vary due to an unpredictable level depending on the situation. Thus, it is a big problem in designing a receiver having excellent jitter tolerance characteristics.
The above-mentioned problems in the conventional technology and the awareness of the challenges related thereto are not obviously known to the persons who skilled in the art of the present invention. Therefore, the present invention shall not be deemed to be obvious based on this awareness.